1. Field of the Invention
The present invention relates to computing systems, and more particularly, to processing network information.
2. Background of the Invention
Conventional computing systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computing system is often referred to as a host system. The term computing system/host system as used throughout this specification, includes network servers.
Host systems (or servers) are used in various applications and environments, including networks and storage area networks (“SAN”). Servers typically communicate with each other using networks. SANs are commonly used to store and access data. SAN is a high-speed sub-network of shared storage devices, for example, disks and tape drives.
Host systems often communicate with other devices via network adapters (may also be referred to as “controllers”). The network adapters can be coupled to a host system via an interface (or by other means), for example, the “PCI” (or PCI-X/PCI-Express) bus interface, or the Hyper Transport interface. The standard bus specifications are incorporated herein by reference in their entirety. Different types of adapters are currently used by host systems, for example, host channel adapters (HCAs) and host bus adapters (HBAs).
Traditionally adapters have been either very simplistic in design or very complex. The simplistic design has been used where the adapter simply moves all the network information (i.e. header and data) to a host and performs very little analysis except in some cases, checking cyclic redundancy codes (CRCs).
In complex designs, adapters have been designed to offload most host processing. The complex design adapters often have one or more processor or complex state machines. The adapters can process network packets and need minimal host supervision. The goal for the complex adapter design is to save host processor cycles and power. However, host processors are becoming very powerful and with emergence of multi-core/multi-threaded processors, the need to save host processor cycles has diminished.
Therefore, what is needed is an optimum adapter design/process that can efficiently process network packets.